1. Field of the Invention
The present invention relates to a semiconductor device having a MISFET and to a method for fabricating the same.
2. Description of the Related Art
As miniaturization has been pursued in the field of semiconductor devices, the trends toward higher-speed operation and lower power consumption have been rapidly accelerated in recent years. In step with these trends, a diffusion profile in a MISFET has been changing significantly. A recent MISFET fabrication process is more complicated and includes an increased number of mask steps than a conventional MISFET fabrication process.
FIG. 7 is a cross-sectional view of a conventional semiconductor device. For the simultaneous illustration of semiconductor elements of different conductivity types included in the semiconductor device, an example is shown in the drawing where a region to be formed with an n-channel MISFET (hereinafter referred to as an NMIS formation region) and a region to be formed with a p-channel MISFET (hereinafter referred to as a PMIS formation region) are provided in the semiconductor device and these regions are isolated by a trench isolation insulating film 1102 formed in a semiconductor substrate 1101.
In the conventional semiconductor device, a p-well region 1101a is formed on the NMIS formation region of the semiconductor substrate 1101 and an n-channel MISFET is provided over the p-well region 1101a, while an n-well region 1101b is formed on the PMIS formation region of the semiconductor substrate 1101 and a p-channel MISFET is provided thereover.
A conventional n-channel MISFET comprises: a gate insulating film 1115a provided on the p-well region 1101a; an n-type gate electrode 1103 provided on the gate insulating film 1115a; and sidewalls 1111a composed of an insulator provided on each of the side surfaces of the n-type gate electrode 1103. The p-well region 1101a is provided with: a p-type threshold control layer 1105 formed in a channel region immediately under the gate insulating film 1115a; n-type lightly doped diffusion layers 1107 formed immediately below the edge portions of the n-type gate electrode 1103 in such a manner as to sandwich the p-type threshold control layer 1105 therebetween; n-type heavily doped diffusion layers 1112 formed laterally below the n-type gate electrode 1103 and the sidewalls 1111a; and p-type pocket diffusion layers 1108 formed under the n-type lightly doped diffusion layers 1107. Silicide layers 1114 and 1118 are further formed on the n-type gate electrode 1103 and each of the n-type heavily doped diffusion layers 1112, respectively.
A conventional p-channel MISFET comprises: a gate insulating film 1115b provided on the n-well region 1101b; a p-type gate electrode 1104 provided on the gate insulating film 1115b; and sidewalls 1111b composed of an insulator provided on each of the side surfaces of the p-type gate electrode 1104. The n-well region 1101b is provided with: an n-type threshold control layer 1106 formed in a channel region immediately under the gate insulating film 1115b; p-type lightly doped diffusion layers 1109 formed immediately below the edge portions of the p-type gate electrode 1104 in such a manner as to sandwich the n-type threshold control layer 1106 therebetween; p-type heavily doped diffusion layers 1113 formed laterally below the p-type gate electrode 1104 and the sidewalls 1111b; and n-type pocket diffusion layers 1110 formed under the p-type lightly doped diffusion layers 1109. Silicide layers 1120 and 1122 are further formed on the p-type gate electrode 1104 and each of the p-type heavily doped diffusion layers 1113, respectively.
In the conventional semiconductor device described above, the p-type threshold control layer 1105 and the n-type threshold control layer 1106 are for adjusting the respective thresholds of the n-channel MISFET and the p-channel MISFET to desired values and are formed by well-known ion implantation using a mask. Each of the concentration of a p-type impurity contained in the p-type threshold control layer 1105 and the concentration of an n-type impurity contained in the n-type threshold control layer 1106 is 1×1012 atoms/cm2 or less. The optimum value of the impurity concentration in each of the threshold control layers differs depending on the gate length and the thickness of the gate insulating film.
On the other hand, the p-type pocket diffusion layers 1108 and the n-type pocket diffusion layers 1110 are for reducing short channel effects occurring in the n-channel MISFET and the p-channel MISFET and are formed by ion implantation using a mask different from that used for forming the threshold control layers. Each of the p-type impurity concentrations in the p-type pocket diffusion layers 1108 and the n-type impurity concentrations in the n-type pocket diffusion layers 1110 is about 1×1013 atoms/cm2.
A conventional semiconductor device as described above is disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2002-270824.